Analog-to-Digital Converter (ADC) serves as the core bridge connecting the real analog world with digital systems. It converts continuously varying analog voltage signals into discrete digital signals that processors can recognize. Whether in industrial measurement, audio acquisition, motor control, or high-speed signal processing, the performance of an ADC directly determines the upper limit of system accuracy.
For beginners, the dense terminology and parameters in chip datasheets often form the first barrier to entry. This article is based on Texas Instruments’ (TI) classic ADC specification terminology framework. Starting from fundamental principles, it breaks down key ADC terms into six modules: architecture basics, timing and sampling, input characteristics, static accuracy, dynamic performance, digital encoding and interface. We will explain step by step the physical meaning, underlying principles, and practical value of each term, helping you build a complete knowledge system for ADCs.
1. Fundamentals: Three Mainstream ADC Architectures and Their Key Differences
Before diving into specific terms, we must first understand the three dominant ADC architectures—Successive Approximation Register (SAR), Pipeline, and Delta-Sigma (ΔΣ). Nearly all differences in ADC performance parameters stem from the working principles of these three architectures, and most technical documentation revolves around them.
| Architecture | Core Working Principle | Key Features | Typical Applications |
|---|---|---|---|
| SAR (Successive Approximation) | Uses capacitor arrays and a successive approximation register to compare input voltage against reference voltage using binary search. One conversion completes per sample, with bit decisions made sequentially | Single-cycle conversion, extremely low latency, low power consumption, medium speed and resolution (8–18 bits, typically <10MSPS) | Industrial control, multiplexed channel switching, portable instruments, power monitoring |
| Pipeline | Composed of multiple cascaded stages; each stage processes 1–2 bits in parallel, passing results forward. Multiple conversions occur simultaneously across stages | High speed and high resolution, high throughput, fixed pipeline cycle delay | High-speed data acquisition, video processing, broadband communication, radar signal sampling |
| ΔΣ (Delta-Sigma) | Employs oversampling + modulator + digital filter architecture. Samples input signal repeatedly and averages results via FIR/IIR digital filters to produce final output | Ultra-high resolution, low speed, long acquisition time, inherent group delay, excellent quantization noise suppression | Precision DC measurements, audio acquisition, industrial weighing, temperature sensing—low-frequency, high-precision scenarios |
In short: choose SAR for fast “snapshot”-style sampling and frequent channel switching; use pipeline ADCs for ultra-high-speed, high-frequency signal capture; select ΔΣ when ultimate precision is required and speed is not critical. This understanding forms the foundation for interpreting all subsequent performance specifications.
2. Timing and Sampling Terms: The “Time Ruler” of ADCs
These terms define the timing behavior, sampling capability, and response speed of an ADC. They are essential for hardware design and timing matching—the first concepts beginners should master.
1. Acquisition Time
Acquisition time is the duration required for an ADC to complete one valid signal sampling. It refers to how long it takes for the sampling capacitor to charge and capture the input voltage after the sampling switch closes.
- SAR-type: Determined by the charging speed of the sampling capacitor. Timing starts upon receiving the sample command. Only one sampling event occurs per conversion, so acquisition time is very short.
- Pipeline-type: Triggered by external clock edges, capturing differential signals immediately following input transitions. Acquisition time corresponds to a single sampling period.
- ΔΣ-type: Requires multiple samples averaged through digital filtering, resulting in much longer acquisition times than the other two types. When handling step inputs or switching channels, additional waiting time is needed for the filter to refresh.
Practical Significance: Acquisition time determines the fastest-changing input signal an ADC can handle. It also defines the minimum wait time required during multiplexed channel switching.
2. Aperture-Related: Aperture Delay and Aperture Jitter
These parameters determine ADC sampling accuracy for high-frequency signals and are critical metrics for high-speed applications.
- Aperture Delay: The time difference between the active edge of the external sampling command (usually at 50% amplitude) and when the ADC actually captures the input signal—an inherent hardware delay.
- Aperture Jitter: The standard deviation of aperture delay across repeated samplings, representing random error in sampling instants. Often mistaken for input noise, it directly degrades SNR (Signal-to-Noise Ratio). The impact of jitter on SNR follows this formula:SNR=20 \log_{10}\left(\frac{1}{2 \pi f t_j}\right)where f is the input signal frequency, and t_j is total jitter (root-sum-square of aperture jitter and clock jitter).
Practical Significance: Higher input frequencies result in larger sampling errors due to aperture jitter. For example, even picosecond-level jitter can cause significant accuracy loss when sampling signals above 1 MHz.
3. Sample Rate vs Conversion Rate
- Sample Rate: The rate at which the ADC completes consecutive conversions, measured in samples per second (SPS) or Hz. It determines the maximum bandwidth of signals the ADC can process. According to Nyquist’s theorem, the sample rate must be more than twice the highest frequency component of the input signal to reconstruct it without distortion.
- Conversion Rate: The maximum frequency at which the ADC outputs conversion results. For SAR ADCs, conversion rate equals sample rate. For ΔΣ ADCs, it equals the modulator frequency divided by the decimation ratio.
4. Conversion Time
The time taken by the ADC to convert the captured analog voltage into a digital result after sampling is complete. Note: this does not include acquisition time. For SAR and pipeline ADCs, conversion time is much shorter than throughput time. For ΔΣ ADCs, conversion time strongly depends on the depth of the digital filter.
5. Throughput Rate and Throughput Time
Throughput time is the total time required for a full cycle: “sampling → conversion → data ready.” Throughput rate is its reciprocal, indicating the actual data output capability of the ADC under continuous operation. This is the key metric for measuring real-world efficiency—not just raw conversion speed.
6. Latency / Delay
The total time from the start of input signal sampling to the availability of the corresponding digital output. Two main types exist:
- Cycle Latency: Number of complete clock cycles between the start of one conversion and the next. SAR ADCs usually have zero or single-cycle latency; pipeline ADCs have fixed multi-cycle latency.
- ΔΣ Latency: Determined by the group delay of internal digital filters—the number of conversion cycles it takes for a signal to pass through the filter. Must be considered during channel switching or power-up. Audio-grade ΔΣ ADCs may have latencies reaching tens of sample periods.
7. Settling Time
Specific to ΔΣ ADCs, this is the response time of the digital filter to a step input—the number of conversions required for the output to converge within specified accuracy after an input jump. After power-on, channel switching, or sudden input changes, accurate results can only be obtained after settling time has elapsed.
3. Analog Input Characteristics: The “Front-End Interface Rules” of ADCs
These terms define hardware requirements for ADC input signals and serve as the basis for front-end analog circuit design, directly influencing topology and component selection.
1. Analog Bandwidth
The input signal frequency at which the ADC’s output amplitude drops by 3dB relative to the input. Represents the upper frequency limit the ADC can handle. Note: Analog bandwidth ≠ sample rate. Many high-speed ADCs have analog bandwidths far exceeding their Nyquist frequency, enabling undersampling applications.
2. Input Types: Single-Ended, Differential, Pseudo-Differential
Basic hardware configurations for ADC inputs, differing significantly in noise immunity and application suitability:
- Single-Ended Input: One signal pin referenced to ground. Simple structure but weak common-mode interference rejection. Suitable only for low-noise, short-distance signal acquisition.
- Differential Input: Includes positive (AIN+) and negative (AIN−) pins. Output depends on the voltage difference between the two. Both signals vary symmetrically (one increases while the other decreases). Offers strong common-mode noise rejection and allows high dynamic range with small swing. Standard for ΔΣ and pipeline ADCs.
- Pseudo-Differential Input: Also uses two pins, but the negative pin accepts only small-range voltages (a few hundred mV), serving as a reference for the positive pin. Used primarily to eliminate small common-mode offsets and minor signal errors. Cannot handle large differential swings like true differential inputs.
3. Input Voltage Range Terminology
- Absolute Voltage Range: Maximum/minimum voltage limits (relative to ground and analog supply) that ADC input pins can withstand. Exceeding this range risks device damage—even with differential inputs, individual pin voltages must stay within absolute limits.
- Full-Scale Range (FS/FSR): The maximum input voltage range the ADC can digitize correctly, determined by internal or external reference voltage. For an n-bit ADC:FS = 2^n × \text{Ideal Code Width (1LSB)}For example, a ±2.5V bipolar-input ADC has an FSR of 5V.
- Unipolar/Bipolar Input Mode: Unipolar supports only positive voltages (0~VREF); bipolar supports both positive and negative (e.g., ±2.5V), accommodating different signal types.
4. Input Impedance and Input Capacitance
- Common-Mode Input Impedance/Capacitance: Impedance/capacitance of a single analog input pin to ground.
- Differential Input Impedance/Capacitance: Impedance/capacitance between the positive and negative differential input pins.
Practical Significance: Input impedance affects driver requirements—higher impedance means less demand on the signal source. Input capacitance impacts sampling circuit bandwidth and charging time, making it a key parameter for high-speed circuit matching.
5. Common-Mode Characteristics and CMRR
- Common-Mode Voltage (V_{CM}): Average of the two differential input voltages: V_{CM}=(AIN+ + AIN−)/2.
- Common-Mode Rejection Ratio (CMRR): Measures the ADC’s ability to suppress common-mode signals at the differential inputs. Defined as the ratio of change in common-mode input to the resulting change in digital output code, expressed in dB. Higher CMRR indicates stronger resistance to common-mode interference.
4. Static Performance Parameters: The “DC Accuracy Scale” of ADCs
Static parameters describe ADC accuracy under DC or near-DC conditions. These are crucial selection criteria for precision measurement and DC signal acquisition, with all parameters based on the Least Significant Bit (LSB) unit.
1. Fundamental Units: LSB and MSB
- Least Significant Bit (LSB): The smallest analog input signal an ADC can resolve—corresponding to the rightmost bit in the digital code. Ideal code width (1LSB):1LSB = \frac{FS}{2^n}where n is the nominal ADC resolution and FS is the full-scale range. For example, a 10-bit ADC with 5V FSR gives 1LSB ≈ 4.88mV.
- Most Significant Bit (MSB): Leftmost bit in the digital code, determining magnitude. In bipolar ADCs, it often acts as the sign bit.
2. Offset Error
Voltage deviation between the ideal first code transition point and the actual one—essentially a horizontal shift of the entire transfer curve.
- In unipolar ADCs: Deviation of the first code transition near 0V from its ideal position.
- In bipolar ADCs: Deviation of the output code from the ideal mid-scale code at zero input.
Offset error can be corrected via hardware or software calibration. Its temperature drift (in ppm/°C) determines accuracy stability over temperature.
3. Gain Error
Deviation between the ideal slope of the transfer function and the actual slope. Appears as a discrepancy between the actual output code and ideal full-scale code at maximum input. Calculated after removing offset error, gain error is independent of offset.
Like offset, gain error can be calibrated out. Its temperature drift is a critical consideration in high-precision systems.
4. Differential Nonlinearity (DNL)
Difference between actual code width and ideal 1LSB width—describing whether each digital code represents a uniform analog voltage interval.
- Ideally, DNL = 0LSB.
- If DNL < -1LSB, missing codes occur—some digital codes never appear, causing jumps in output as input increases.
- If DNL > 1LSB, wide codes appear, reducing local resolution.
Practical Significance: DNL is vital for imaging, closed-loop control, and video applications—directly affecting local linearity and monotonicity.
5. Integral Nonlinearity (INL)
Maximum deviation of the actual transfer curve from a straight line (after correcting offset and gain errors)—measures overall linearity, in units of LSB. INL accumulates DNL errors; worse DNL generally leads to worse INL.
Two fitting methods: endpoint fit and best-fit. Best-fit INL error is typically half of endpoint fit, and is key for imaging and precision measurement.
6. Monotonicity and Missing Codes
- Monotonicity: As analog input increases/decreases continuously, the digital output either stays constant or increases/decreases accordingly—never reverses. Essential for automatic control and closed-loop systems to prevent oscillation.
- No Missing Codes: All 2^n possible digital codes appear as input sweeps full scale. An ADC without missing codes is always monotonic.
7. Total Unadjusted Error (TUE)
Total deviation of the ADC’s digital output from the ideal value, combining offset, gain, and INL errors. Represents the upper limit of DC accuracy without any calibration.
5. Dynamic Performance Parameters: The “AC Performance Ceiling” of ADCs
Dynamic parameters describe ADC performance under AC signal inputs—critical for high-frequency sampling, audio processing, and communications. All values are derived from Fast Fourier Transform (FFT) analysis.
1. Quantization Noise and Signal-to-Noise Ratio (SNR)
- Quantization Noise: Inherent ±½LSB uncertainty when converting continuous analog signals to discrete digital codes. Ideal RMS value: q/\sqrt{12}, where q is 1LSB voltage.
- SNR: Ratio of RMS power of the input AC signal to noise power (excluding harmonics and DC), in dB. For ideal full-scale sine wave input:SNR_{ideal}=6.02n+1.76\,\text{dB}where n is the nominal ADC resolution. For ΔΣ ADCs, higher oversampling ratios improve SNR.
2. Signal-to-Noise and Distortion (SINAD)
Ratio of RMS power of the fundamental signal to the sum of noise and harmonic distortion powers, in dB. SINAD accounts for both noise and distortion, offering a more realistic view of AC performance:
where P_S is fundamental signal power, P_N is noise power, and P_D is harmonic distortion power.
3. Effective Number of Bits (ENOB)
Actual effective resolution achieved by the ADC under AC input—a key parameter often overlooked by beginners. The advertised “16-bit” resolution is theoretical, whereas ENOB reflects usable resolution. Related to SINAD by:
For example, a 16-bit ADC with 86dB SINAD yields only ~14-bit ENOB—meaning only 14 bits are practically usable. ENOB is central to oscilloscopes, waveform recorders, and spectrum analyzers.
4. Total Harmonic Distortion (THD)
Root-sum-square of harmonic power relative to fundamental signal power, in dBc (relative to carrier) or dBFS (relative to full scale). Primarily caused by INL errors, THD reflects nonlinear distortion—critical for audio and geophysical exploration.
5. Spurious-Free Dynamic Range (SFDR)
Difference in dB between the amplitude of the fundamental signal and the largest spurious component (harmonic or non-harmonic) in the FFT spectrum. SFDR indicates the ADC’s ability to detect small signals in the presence of large ones—key for communication and video systems.
6. Other Key Dynamic Parameters
- Intermodulation Distortion (IMD): Power ratio of intermodulation products to fundamentals when two closely spaced sine waves are input. Evaluates distortion under multi-tone conditions—important for broadband communication and radar.
- Full-Power Bandwidth (FPBW): Frequency at which reconstructed output amplitude drops by 3dB under full-scale input—represents maximum operating frequency at full scale.
- Effective Resolution Bandwidth: Highest input frequency at which SNR drops by 3dB—defines bandwidth limit for AC sampling.
6. Digital Encoding and Interface Terms: The “Digital Output Rules” of ADCs
These terms define how ADCs encode output codes and communicate with processors—essential for software data parsing and hardware interface design.
1. Common Digital Encoding Formats
Output coding depends on input type (unipolar/bipolar). Beginners need only know three common formats:
- Unipolar Straight Binary (USB): For unipolar inputs only. 0V maps to all-zeros (0000), full-scale minus 1LSB maps to all-ones (1111). Default for unipolar ADCs.
- Binary Two’s Complement (BTC): Most common for bipolar inputs. MSB is sign bit: 0 for positive, 1 for negative. Zero maps to 0000, positive full-scale to 0111, negative full-scale to 1000. Fully compatible with processor signed integers—no extra conversion needed.
- Bipolar Offset Binary (BOB): For bipolar inputs. Negative full-scale maps to all-zeros (0000), zero to midpoint (1000), positive full-scale to all-ones (1111). MSB can act as sign indicator (1 = non-negative, 0 = negative).
2. Digital Communication Interfaces
- SPI Interface: 3- or 4-wire serial interface. ADC operates as slave, initiated by master. High-efficiency point-to-point communication with fast rates—dominant for most medium/high-speed ADCs.
- I2C Interface: 2-wire serial interface supporting multiple devices with built-in addressing. Slower than SPI, suitable for low-speed, low-pin-count precision ADCs.
7. Auxiliary and Environmental Terms
Beyond core performance, these terms affect engineering usability and are important supplements for hardware design and system selection:
- Calibration Functions: Include self-calibration, background calibration, and system calibration. Self-calibration disconnects input internally to correct offset/gain; background calibration runs automatically during operation; system calibration corrects errors across the entire signal chain including front-end circuits.
- Power Supply Rejection Ratio (PSRR): Measures ADC’s immunity to power supply fluctuations, in dB. Higher PSRR means better noise rejection and relaxed power supply design requirements. Includes DC and AC PSRR.
- Power Consumption: Includes operating power, hardware/software shutdown modes—critical for battery-powered and portable devices.
- Temperature Characteristics: Operating/storage temperature ranges, maximum junction temperature, and parameter drift coefficients—all determining operational stability under extreme conditions.
Summary: Core Selection Logic for Beginners
After reviewing all terms, remember this core selection logic to quickly match ADCs to your application:
- Precision DC Measurement: Prioritize static parameters (INL, DNL, offset error). Choose ΔΣ ADCs. Focus on ENOB and noise performance.
- Industrial Control / Multiplexed Channel Switching: Prioritize acquisition time, latency, monotonicity. Choose SAR ADCs. Pay attention to DNL and channel-switching settling time.
- High-Frequency / High-Speed Acquisition: Prioritize dynamic parameters (SNR, SFDR, ENOB), sample rate, analog bandwidth. Choose pipeline ADCs. Emphasize aperture jitter and full-power bandwidth.
Download Link for TI Application Report – Glossary of Specifications and Performance Characteristics for Analog-to-Digital Converters: https://www.123865.com/s/2Y9Djv-gJddH?pwd=d4m2#