Hi everyone, I’d like to ask a question about flyback power supply PCB design.
Currently on the board, the trace from the switching MOSFET’s drain to the transformer primary winding was routed a bit too thin. Now, to increase the current-carrying capacity of this path and improve heat dissipation, I plan to open the solder mask on this trace and stack solder on it, effectively increasing the trace thickness.
I’d like to ask, will opening the solder mask to thicken the trace at the high-voltage switching node of the MOSFET drain have a significant impact on the power supply’s radiated EMI? Since this effectively increases the copper area of the switching node, could it actually worsen radiated emissions? Are there any design details I should pay attention to?
This spot is the main EMI source, and routing a smaller loop can reduce EMI. I want to increase the current capacity and heat dissipation, but I’m not sure if it will increase EMI. Has anyone tried this!
It will definitely have a measurable impact. The drain of the MOSFET is your primary high dV/dt node. By exposing the copper and piling up solder, you are effectively increasing the surface area and altering the 3D geometry of the trace. This directly increases the parasitic capacitance to the chassis or nearby planes, which will pump up your common-mode noise. If you must do it for a quick bench prototype, keep the exposed area as small as possible. But honestly, tweaking the snubber or just respinning the board with a tighter layout is a much safer bet for passing EMC compliance.
There are two sides to this issue. Opening the solder mask for tinning does indeed increase the effective copper area of the switching node. Theoretically, this increases the parasitic capacitance to ground, and with dv/dt unchanged, the displacement current i=C·dv/dt will increase, which could worsen radiated emissions.
However, the actual effect depends on how thin your original trace was. If the original trace was already severely overheating, it indicates excessive trace resistance, and the ringing and spikes of the switching waveform may have already degraded due to resistive voltage drop. In this case, thickening the trace to reduce impedance might actually improve the switching waveform quality, offsetting the negative effects of the increased area.
I suggest you first compare the measured waveforms at the Drain before and after the solder mask opening, focusing on changes in ringing amplitude and frequency. Additionally, try to limit the exposed area to just the trace body; don’t connect it to large copper pours, and keep the increase in “effective area” under control.
Bro, if you drew the primary side traces too thin, just redo the layout! Relying on piling on solder to increase current capacity is a total myth anyway. Solder’s conductivity is only about a tenth of copper’s—how thick would you have to pile it on to get the same current-carrying capacity? Plus, that Drain trace is an EMI hotspot to begin with. Keeping the loop small is one thing, but you also need to keep the node area as small as possible. By forcibly enlarging it just for heat dissipation now, you’ll end up making a trip to the EMC lab later, and the test fees alone will cost enough to pay for ten board spins. Take it from me: widening the traces and using 2oz copper is the right way to go.
I’ve tried this exact “fix” before to lower temps on a 65W flyback adapter. Did it worsen EMI? Absolutely, especially in the 30-50 MHz range. The thick, uneven wave solder acted like a perfect little broadside antenna. We ended up having to increase the gate resistor slightly to slow down the switching edge just to pass the radiation test, which totally defeated the thermal benefits we gained from the solder in the first place! Don’t rely on it.
From a radiation mechanism perspective, as long as the solder mask opening is strictly controlled and the horizontal area of the original trace is not enlarged, the impact on EMI is actually quite minimal.
The radiated emissions from switching nodes are essentially caused by the loop antenna effect formed by high dv/dt and di/dt loops, as well as the common-mode coupling through the node’s parasitic capacitance. Thickening the solder plating only increases the vertical thickness of the trace and does not increase the effective radiation area in the horizontal direction; on the contrary, because the conductor cross-sectional area increases, the trace’s parasitic inductance and resistance slightly decrease, which can theoretically suppress switching spikes a bit.
What you really need to watch out for is solder overflow when hand-soldering, which effectively widens the trace and expands the copper area of the switching node—this is what actually leads to increased radiation in the high-frequency band. Additionally, it is recommended to maintain sufficient clearance between the trace and the reference ground to avoid increasing parasitic capacitance.