STM32-Based Synchronous Rectification Buck-Boost Digital Power Supply Open Source

[zeruns]

How much voltage drop is there at the terminal block? (Measure under load)
You can use a multimeter to directly measure both ends of a single wire to check the wire voltage drop. If your multimeter is accurate, then 180mΩ is very high. The wire might be the issue, possibly a falsely labeled one.

[muzi1111]

1. The waveform measured from the MCU looks fine, but when the voltage exceeds 20V, the drive output waveform looks exactly like the VS-to-ground waveform, just like the blue section in the picture I uploaded earlier.

2. I have hardware protection, but when it kicks in, this cycle should be at a low level. The actual waveform shows three spike-like pulses instead, so hardware protection can be ruled out.

3. I suspected the inductor was approaching saturation, so I swapped it for one with a higher saturation current. The exact same phenomenon occurred—the problem always appears when the voltage exceeds 20V.

4. I increased the bootstrap capacitor, swapping the 100nF for a 470nF one. It improved slightly, with the issue only showing up at 26V, but when I increased it further to 1uF, the problem still occurred at 26V.

5. I added an RC snubber circuit using 4.7Ω + 0.8nF, which also helped a bit. With the AP68N06G as the high-side MOSFET, it can go up to 40V, but for the CSD19531Q5A, it doesn’t help at all.

6. I’ve tried a lot of methods, but none of them have managed to solve this issue. Does anyone have any new ideas?

[muzi1111]

1. The behavior is the same with loads of 20Ω and 6Ω. I actually used a 100nF bootstrap capacitor, and later swapped the 100nF for a 470nF one, which improved things slightly—the issue didn’t appear until 26V. But increasing it to 1uF, the problem still occurs at 26V
2. I switched to an inductor with a higher saturation current, but the behavior remained the same. Lowering the frequency to 40kHz didn’t help either; the problem is exactly the same,
3. Suppressing spikes and ringing: I added an RC snubber circuit using 4.7Ω + 0.8nF, which also had a slight effect. (With the AP68N06G as the high-side MOSFET, it can reach 40V, but for the CSD19531Q5A, it doesn’t help at all.)
4. Control method improvement: I want to test the circuit to ensure it’s issue-free before closing the loop; otherwise, my gain is uncertain (at low voltages it matches the preset, but at high voltages the gain becomes uncertain). Closing the loop like this wouldn’t be able to save my circuit anyway, right?

[ABC]

Bro, your cross-validation troubleshooting on this one was beautifully done, and your variable control was spot on. After eliminating the interfering factors one by one and combining the 5 pieces of info you provided—especially Point 5 (the AP FET can hold up to 40V, while the CSD FET craps out at 26V)—this is the most crucial clue to cracking the case!

The root cause behind the phenomenon can be pinned down to this: FETs like the CSD19534/19531 switch way too fast (extremely low Q_g and R\_{DS(on)}). The massive dv/dt and di/dt generated as a result cause severe EMI and transient voltages at high voltage, completely knocking your “driver IC” out cold. The older AP FETs, on the other hand, actually ended up serving as a “snubber” by sheer coincidence, thanks to their larger parasitic capacitance and slower switching.

Even though the waveform coming out of the MCU is perfect, the driver IC is “going on strike” in the harsh power environment. For this situation, I suggest you hit it with some strong medicine from the following four directions:

1. Force the CSD FET to “slow down” (the most critical step)

A good horse needs a good saddle; if a super-fast switching FET has even a slight flaw in its PCB layout (especially loop parasitic inductance), it will produce absolutely terrifying ringing.

• Countermeasure: Check if there is a gate resistor (Gate Resistor, R_g) in series between your driver output and the CSD FET’s Gate. If there isn’t, or if the value is extremely small (like 0Ω or 2.2Ω), immediately cut the trace and solder a 10Ω to 22Ω resistor in series.

• Purpose: To forcefully reduce its turn-on and turn-off speed, weakening the dv/dt. During the testing phase, it’s better to sacrifice a little bit of switching loss causing the FET to get slightly hot, just to get the waveform stabilized first.

2. Clamp the “negative voltage spike” at the VS node (prevents the driver IC from crashing)

During the dead time (when the inductor current is freewheeling through the bottom FET’s body diode), or at the exact moment the top FET switches off at high speed, the VS (switch node) gets pulled down to an extremely deep reverse negative voltage by the parasitic inductance.

• Hidden danger: The VS pin of most half-bridge/high-low side driver ICs (like IR2104, EG3012, etc.) can only withstand a very limited negative voltage (typically -2V to -5V transient). If this is exceeded, the high-side logic circuitry inside the driver IC will instantly go haywire, outputting the “glitchy spikes” you’re seeing or forcing a direct shutdown.

• Countermeasure: Between the driver IC’s VS pin and the driver IC’s logic ground (PGND), parallel a Schottky diode with leads as short as possible (anode to PGND, cathode to VS). I recommend using a BAT54 or SS14. This forcefully clamps the negative voltage to around -0.5V, protecting the driver IC.

3. Upgrade the voltage rating and current limiting of the bootstrap diode

You mentioned that swapping in a larger bootstrap capacitor gave a slight improvement, which indicates the high side is indeed on the verge of “starving for juice”.

• Hidden danger: The bootstrap diode used in your schematic (though it’s a bit blurry, I can roughly guess) is an SS14. The SS14’s voltage rating is only 40V! When your input voltage reaches 26V, combined with the ringing peaks generated by the high-speed switching, it’s absolutely possible to momentarily exceed 40V. Once it breaks down or experiences avalanche leakage, the charge in the bootstrap capacitor gets instantly drained, and the high-side FET will shut down due to undervoltage lockout (UVLO).

• Countermeasure: 1. Swap the SS14 for a diode with a higher voltage rating, like the SS110 (100V) or an ultra-fast recovery diode (like ES1B, US1M, etc.).

  2. Between the bootstrap diode and the bootstrap capacitor, add a 2.2Ω ~ 4.7Ω current-limiting resistor in series. This effectively prevents the high-frequency noise during switching moments from shooting straight into the driver IC’s VDD supply through the bootstrap capacitor.

4. Check the driver IC’s power supply and “Ground Bounce”

Even though the MCU output is good, the signal received by the driver IC is referenced to its own GND.

• Countermeasure: Make sure there is a 0.1uF (100nF) high-frequency decoupling ceramic capacitor between the driver IC’s VCC pin and its GND, and this capacitor must be snug against the driver IC’s pins. If the di/dt causes the power ground to bounce violently, the driver IC will mistakenly think the PWM signal at the input is toggling like crazy.

I suggest your first step should be to try slapping a ~15Ω resistor in series with the top FET’s Gate, and see if the waveform can hold steady at 26V.

[知夏]

The extra information you provided is crucial; it basically rules out a simple DCM issue — the load current differs by more than three times between 20R and 6R, yet the phenomenon is the same, which doesn’t match the characteristics of DCM (with DCM, it should be harder to occur under heavier loads).

Core Issue Diagnosis: It’s Not DCM, It’s Drive Oscillation / Source Inductance Effect Caused by High-Speed MOSFET Switching

The drastically different behavior when you swap MOSFETs is the most crucial clue.

The CSD19531Q5A uses TI’s NexFET process and has extremely fast switching speeds; both its di/dt and dv/dt are very aggressive. The AP68N06G is relatively slower, so the RC snubber can still suppress it, but switching to the CSD19531 overwhelms the snubber.

Here’s exactly what’s happening:

Common Source Inductance Effect

• Your VS node (MOSFET source) trace definitely has parasitic inductance, which could be anywhere from a few nH to tens of nH
• At the moment the CSD19531 turns on, the di/dt is extremely high, generating a voltage drop across the source parasitic inductance: V = Ls × di/dt
• This voltage represents a “raised source potential”, which is equivalent to Vgs being pulled down
• When the di/dt gets large enough, Vgs is dragged directly below the threshold voltage, and the MOSFET is forcibly turned off right after turning on
• After turn-off, the current drops, the di/dt reverses, Vgs rises again, and the MOSFET turns back on… forming an oscillation
• The “spikes” you’re seeing are actually the oscillating waveform of the MOSFET rapidly turning on and off, not a normal conduction platform

This also explains the other phenomena:

• Increasing the bootstrap capacitor helps but only to a limited extent: A larger bootstrap capacitor makes the drive power supply “stiffer”, making Vgs less prone to collapsing. But the root cause is the excessive di/dt, so upgrading to 1uF hits a bottleneck
• Lowering the frequency doesn’t help: This is a switching transient issue and has nothing to do with the cycle length
• Switching to an inductor with a higher saturation current doesn’t help: The inductor isn’t saturating; if the inductance value hasn’t changed, the ripple magnitude hasn’t either
• DS RC snubber is ineffective for the CSD19531: RC snubbers mainly suppress dv/dt, whereas the main culprit here is the source inductance effect caused by di/dt, so the DS capacitor has limited impact

How to Fix It

① Most Direct and Effective: Add a Series Gate Resistor to Slow Down Switching (Highly Recommended to Try First)

Add a resistor in series with the CSD19531’s gate, try between 10Ω~100Ω, to slow down the switching speed and bring the di/dt down.

Driving a high-speed MOSFET like NexFET directly without a gate resistor makes it very easy to blow the driver or cause oscillation. What is your current drive resistor R1? Looking at the schematic, is R1 marked as 10R? If it’s already 10Ω, try bumping it up to 22Ω or 47Ω; you should see a significant improvement.

The trade-off is a slight increase in switching losses, but for your current operating condition of 100KHz and tens of volts, it is perfectly acceptable.

② Optimize the Drive Loop to Reduce Parasitic Inductance

• Keep the trace from the driver IC output to the MOSFET gate as short and wide as possible
• Minimize the loop area enclosed by the gate drive return path (drive ground → source → gate → driver output)
• Place the bootstrap capacitor as close as possible to the VB and VS pins of the driver IC; avoid long traces

③ Add a Small Capacitor or Clamp Between Gate and Source

• Add a small capacitor of a few hundred pF (e.g., 220pF~1nF) in parallel across GS; this can suppress gate oscillation, but it will also slow down the switching speed, similar to the effect of a gate resistor
• Or add a pair of back-to-back Zener diodes (e.g., 12V+15V) in parallel to directly clamp Vgs within a safe range, preventing overvoltage and oscillation

④ Check the Status of the Boost-Side MOSFET

You have a Buck-Boost topology; is the Boost-side low-side MOSFET Q2 normally off, or is it also switching synchronously? If Q2 is also turning on, its di/dt can couple through the inductor and complicate the issue. During the testing phase, you can completely turn off the Boost-side MOSFET first and run it only in Buck mode to eliminate interference.

Regarding the Closed-Loop Issue

You’re right; get the open-loop waveform normal first before closing the loop.

Closed-loop control solves the issue of “whether the output voltage is stable”, but it can’t save switching anomalies at the hardware level. If the MOSFET oscillates as soon as it turns on at the hardware level, or even experiences false turn-on / false turn-off, precisely adjusting the duty cycle is useless; the loop might actually become even more unstable due to this abnormal waveform.

First add the gate resistor and adjust the VS waveform into a clean square wave. The gain will naturally be determined, and there’s no rush to calculate the compensation parameters until then.

Try adding a gate resistor first, starting at 22Ω, and go larger if it doesn’t work. See if the waveform above 26V can return to normal.

[songsong-sunny]

Hi, I have a question. When operating in buck mode, the first state is Q1 and Q3 on, Q2 and Q4 off; the second state is Q2 and Q3 on, Q1 and Q4 off. In this case, Q4 remains off all the time, so Q3’s bootstrap capacitor cannot charge to ground and can only charge the SW2 node, causing Q3’s UGS voltage to be insufficient.

[zeruns]

Have you looked at the code? In the actual code, it isn’t continuously on; it has a duty cycle of over 90% to ensure the bootstrap capacitor has time to charge.

[云游僧]

Thanks, expert! I feel like I understand a bit, but not really!

For the first step, when designing it, do we need to determine the buck crossover frequency using a Bode plot test? Or do we rely on simulation software? If we test it, how exactly do we do that in practice? I have the same question for the boost side!

For the fifth step, in the Kadc calculation formula, is Kdiv the voltage gain from our schematic, the 0.062 value? KPWM should be 30000, and I understand Kanalog to be a variable parameter that is adjusted in real time.

For the sixth step, hardware compensation calculation: is there a reference document for the STM32G474? I’d like to understand it further first.

[jjj]

Hi, I have a question. Recently, while studying this project’s code, I saw that ADC1 is configured for four-channel sampling with 4x oversampling. The ADC clock frequency is one-fourth of 170 MHz, which is 42.5 MHz. After checking the manual and the code, I found a 2.5-cycle sampling time, a 12.5-cycle conversion time, and a 0.5-cycle delay. GPT also told me to multiply by 2x4x4, corresponding to the four channels and 4x oversampling.

Based on this calculation, one ADC conversion would take longer than one PWM clock cycle at 181 kHz. Does this mean that a complete four-channel ADC conversion only occurs once every two switching cycles? Did I read or understand something incorrectly, or is it sufficient that the ADC’s 2.5 sampling cycles occur in the middle of the switch-on period?

[ABC]

1. Your calculation is correct: 16 conversions ≈ 5.84 μs, which is indeed slightly longer than the 181 kHz switching period (5.52 μs).

2. But “it takes two switching cycles to complete one four-channel conversion” is not a problem: the digital power supply control loop only cares about sampling instant alignment (usually the PWM midpoint); it does not require all conversions to complete within a single cycle. The current-loop channels are synchronized as a priority, and the remaining channels can be sampled in rotation.

3. The statement “2.5 cycles in the middle of the switch-on period” is inaccurate: 2.5 cycles is the sample-and-hold time (≈59 ns), not a window that can be positioned. What needs to be positioned is the trigger instant—use a timer TRGO signal to trigger the ADC so it samples at the midpoint.

4. If you want to scan everything within one cycle, that is simple too: reduce oversampling from 4x to 2x, and 8 conversions ≈ 2.9 μs, which fits easily.

In short: accurate sampling timing is far more important than scanning speed. In ADC timing design for digital power supplies, 90% of the work is making that trigger edge land precisely at the correct PWM phase.

[jjj]

Got it, got it — that makes sense. Thanks for clearing that up

[hhhhh]

The ADC acquisition I replicated is also inaccurate. For some of the data, modifying the software reduced the error. It’s possible there’s an error in my layout.

[zeruns]

Did you redraw the board yourself?

[xm051201]

What’s going on with the lack of output?

[zeruns]

Check whether there are any soldering issues, including cold solder joints, and inspect the sampling section for any problems with the power supply or output.