How exactly do you mean, buddy? I don’t understand why it can’t operate unloaded in open-loop mode.
If there are no issues with the welding, could the inaccurate voltage and current readings collected by the ADC be due to a problem with the ADC’s data processing algorithm? Because after I modified some of the code related to numerical processing, the error became significantly smaller.
Go learn the principle of boost yourself. Here’s an AI-generated response for you:
In simple terms, a Boost converter operating under no-load (no load) and open-loop (no feedback control) conditions will cause the output voltage to rise indefinitely, eventually burning out the capacitor, switch, or diode.
Below is a deep dive into the underlying physics:
1. Energy Accumulation: “Only Increase, No Decrease”
The Boost circuit operates in two phases:
- Charging phase: The switch turns on, and inductor L stores energy.
- Discharging phase: The switch turns off, and the inductor L transfers its stored energy, combined with the input voltage V_{in}, to charge the output capacitor C.
Under normal loaded conditions, the energy transferred from the inductor to the capacitor each cycle is dissipated by the load, achieving energy balance.
However, under no-load conditions, the load current is zero. This means that the energy “pumped” from the inductor into the capacitor during each switching cycle has nowhere to go. According to the capacitor energy formula E = \frac{1}{2}CV^2, as energy accumulates continuously, the voltage V must keep rising.
2. Mathematical Model Derivation
In ideal conditions (Continuous Conduction Mode, CCM), the output voltage of a Boost converter is given by:
V_{out} = \frac{V_{in}}{1 - D}
(where D is the duty cycle)
- Open-loop operation: The duty cycle D remains fixed (e.g., D=0.5).
- Conflict between theory and reality: The theoretical formula assumes “dynamic equilibrium.” However, under no-load conditions, due to the absence of output current, the circuit enters Discontinuous Conduction Mode (DCM). In DCM, if the duty cycle is fixed and the load approaches infinity, the theoretical output voltage tends toward infinity.
3. Catastrophic Consequences
Since “infinite voltage” doesn’t exist in real circuits, the system fails when physical limits are exceeded:
- Capacitor breakdown: The output filter capacitor’s voltage rating (VDC) is exceeded, causing it to explode or short-circuit.
- Switch/diode failure: The MOSFET’s V_{ds} or the diode’s reverse voltage rating is exceeded, leading to breakdown.
- Feedback failure: Although you mentioned “open-loop,” even if a feedback circuit exists, if the response is too slow or lacks Over-Voltage Protection (OVP), the voltage spike generated instantly under no-load can still be fatal.
Summary and Preventive Measures
| Characteristic | Behavior | Result |
|---|---|---|
| Energy transfer | Energy is forcibly “pumped” to the output each cycle | Charge accumulates continuously on the capacitor |
| Voltage feedback | Absent (open-loop), cannot reduce duty cycle to lower voltage | Voltage becomes uncontrolled |
| Final outcome | Voltage exceeds component voltage ratings | Hardware destruction |
How is this solved in practical engineering?
- Closed-loop control: Use a PWM controller that automatically reduces the duty cycle D when high voltage is detected.
- Dummy Load: Connect a large resistor in parallel at the output to ensure a small current consumes excess energy, even under no-load conditions.
- Over-Voltage Protection (OVP): Add hardware-level voltage clamping circuits.
You haven’t provided enough information to answer your question—no images, no data, and no detailed description (what modifications were made?).
Recommended reading: https://bbs.eeclub.top/t/topic/109
Designing the loop compensation parameters for a digital Buck-Boost circuit based on the STM32G474 is a process of transforming from continuous domain (analog) design to the discrete domain (digital). The STM32G474, with its high-resolution timer (HRTIM) and built-in mathematical accelerators (FMAC/CORDIC), is particularly well-suited for such high-frequency digital power control.
The calculation and design of digital loop compensation parameters typically involve the following key steps:
Step 1: Obtain the Small-Signal Model of the Power Stage (s-domain)
First, you need to know the continuous-time transfer function G_{vd}(s) (control-to-output voltage) of the plant being controlled—the Buck-Boost power stage.
For a four-switch synchronous Buck-Boost converter, there are generally three operating modes, each with different transfer functions:
- Buck Mode: A minimum-phase system, featuring LC double poles and an ESR zero from the output capacitor.
- Boost Mode / Buck-Boost Mode: A non-minimum phase system. In addition to the LC poles and ESR zero, it includes a Right-Half Plane Zero (RHPZ).
- The RHPZ introduces additional phase lag while increasing magnitude, making the system highly prone to instability.
- The frequency of the RHPZ is typically given by:f_{RHPZ} = \frac{R_{load} \cdot (1-D)^2}{2\pi L}
Critical Point: Your loop crossover frequency (bandwidth) f_c must be designed to be below 1/5 to 1/3 of the worst-case RHPZ frequency to ensure sufficient phase margin.
Step 2: Design the Analog Compensator (s-domain)
Once G_{vd}(s) is known, define the target crossover frequency f_c (typically set to 1/10 of the switching frequency f_{sw}) and desired phase margin (usually between 45^\circ and 60^\circ).
- Voltage Mode Control (VMC): Typically requires a Type III compensator (equivalent to PID, providing two poles and two zeros) to compensate for the 180^\circ phase drop caused by the LC resonance.
- Peak Current Mode / Average Current Mode (CMC): The current loop reduces the inductor dynamics to a first-order system; thus, the outer voltage loop usually only needs a Type II compensator (equivalent to PI).
Assuming a PI controller, its continuous-domain transfer function is:
G_c(s) = K_p + \frac{K_i}{s}
Step 3: Discretization (s-domain → z-domain)
Microcontrollers cannot directly implement s-domain equations; they must be converted into the z-domain. The most common method is the bilinear transform (Tustin’s method), which preserves frequency-domain characteristics well.
Apply Tustin’s substitution:
s \approx \frac{2}{T_s} \frac{1 - z^{-1}}{1 + z^{-1}}
(where T_s is the sampling period of the control loop)
Substitute this into G_c(s) to obtain the digital compensator transfer function G_c(z).
Step 4: Derive the Difference Equation (C Code Implementation)
Convert G_c(z) into a time-domain difference equation—the actual code logic executed on the STM32G474. For a standard incremental PI control, the derived difference equations are:
\Delta u[n] = K_p \cdot (e[n] - e[n-1]) + K_i \cdot T_s \cdot e[n]
u[n] = u[n-1] + \Delta u[n]
- e[n]: Error between current ADC-sampled voltage and reference voltage.
- e[n-1]: Previous error value.
- u[n]: Current computed control output (duty cycle compare value for HRTIM).
- u[n-1]: Previous control output.
Step 5: STM32G474 Hardware Gain Calibration
In a digital system, the calculated K_p and K_i values cannot be used directly as derived from analog design—they must account for ADC quantization gain and PWM conversion gain:
- ADC Gain (K_{ADC}): For example, using a 12-bit ADC with a 3.3V reference and feedback divider ratio K_{div}, the relationship between ADC reading and actual output voltage is:K_{ADC} = \frac{2^{12} - 1}{3.3} \cdot K_{div}
- PWM Gain (K_{PWM}): The HRTIM on the G474 offers extremely high resolution (~170ps). If the HRTIM period register value is PER, the relationship between duty cycle and control input is:K_{PWM} = \frac{PER}{1.0}
The final digital parameters K_{p\_digital} and K_{i\_digital} must be scaled proportionally according to the overall system gain:
K_{digital} = \frac{K_{analog}}{K_{ADC} \cdot K_{PWM}}
STM32G474 Programming Optimization Tips
- Fixed-Point Arithmetic: To achieve ultra-fast response, avoid using
float(even though the G474 has an FPU). Use fixed-point formats like Q15 or Q31, combined with CMSIS-DSP library functions such asarm_pid_q31, or leverage the G474’s FMAC (Filter Math Accelerator) to let hardware automatically compute PI or Type III compensation. - ADC Trigger Mechanism: Use a specific HRTIM event (typically at the midpoint of the PWM cycle) to trigger ADC sampling via hardware. This avoids switching noise and is known as “blanking” or average current sampling.
Thank you, expert, now I understand!
Hey expert, why are the two input terminals of this input current sensing connected like this? Wouldn’t this connection result in a negative output voltage? Could it be because the directions of input and output current flow are opposite? If we define the output current as positive, then the input current would be negative? Also, looking into pin 5 (non-inverting input), aren’t the 100-ohm resistor and the 6.2k resistor in parallel? How should I understand this? Thank you, expert!
- Carefully re-examine the polarity of the voltage generated across the sampling resistor due to current flow.
- Search by yourself for the principle and calculations of operational amplifier differential amplifier circuits (analog electronics fundamentals).
I think I’m not mistaken: 1. The current should flow from VOUT+ → load → VOUT- → GND → VIN- → VIN+, right? 2. When R47=R39 and R43=R41 in a differential op-amp, the output should be Vout = (R47/R43)(0-VIN-). Moreover, combining R41 and R39 essentially results in an inverting amplifier.
Brother, your understanding of the external current loop is slightly reversed. The power supply comes from VIN, with current flowing into VIN+, going through the circuit and reaching GND, then it must return to VIN- via R13 to complete the path back to the negative terminal of the external power source. Since the current flows from GND to VIN-, relative to GND (0V), the voltage at VIN- is actually a negative voltage!
Given that the input signal is a negative voltage, the op-amp is configured in an inverting amplification setup, so the output V_{out} = -62 \times (\text{negative voltage}). A negative times a negative gives a positive, hence the ADC samples a positive voltage.
Regarding your observation about the resistor connected to pin 5—great catch! This is because the equivalent resistance “seen” into the inverting input (pin 6) is the parallel combination of 100 Ω and 6.2 kΩ. To eliminate errors caused by the op-amp’s input bias current, the non-inverting input (pin 5) must also be connected to ground through an equivalent resistance of the same value. In analog electronics, this is called a balancing resistor, a standard practice to improve sampling accuracy.
But if you do this, from the perspective of terminal 5, these two resistors are in parallel, and the equivalent resistance after being connected in parallel is what’s actually connected to terminal 5.
Have you studied the fundamentals of analog electronics?
Learn about Kelvin sensing (Kelvin wires).
I suddenly understood, boss! Because the current through the sampling resistor at the input flows out from GND and into VIN-, VIN- becomes a negative voltage. Therefore, the non-inverting input is connected to GND (0V), while the inverting input is connected to VIN-. The 6.2kΩ resistor above is connected in the standard differential amplifier configuration. Although it appears that both resistors are grounded, R41 and R39 seem to be in parallel, so calling it an inverting amplifier doesn’t seem wrong either.
Hey man, I’d like to ask, doesn’t his power supply method have two types? One is USB-C power delivery and the other is DC jack. And it has a voltage spoofing chip with all three configuration pins left floating, which by default spoofs 20V. That means we can only use either a 100W charger supporting 20V/5A or a DC adapter providing more than 12V to power this board, right?
Maximum spoofing up to 20V, not limited to only 20V; if the charger doesn’t support 20V, it will step down, for example to 15V/12V.
Oh, I see. This means the spoofing chip supports a maximum voltage档位 of 20V, but voltages below 20V are also acceptable. However, it must not be lower than 12V; otherwise, the first-stage buck chip won’t be able to step down the voltage to 12V to power the half-bridge driver and the small fan.
Yes
By the way, man, did you run into any major debugging issues while working on this project? Could you elaborate on a few of the bigger or more common ones?
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Why is buckpwm referred to as period-buck,
while boost is simply called boost?
Is 180-degree phase shifting required?
I’ve already asked dpseek, but the answer is unclear—looking for clarification.