Hi everyone, I’m using the UCC21520 for a rectified-input SPWM, and the high-side waveform has a dip issue. With an input PWM wave, there’s no dip. Is the bootstrap charging time insufficient? How should I fix it? Figure 1 shows the input SP wave with a modulation ratio of 1; when I lower the modulation ratio to 0.6, there’s still a small dip. Figure 2 is the high-side output waveform. Figure 3 is the schematic—please advise.
Figure 1:
Figure 2:
Figure 3:
Let me explain the mechanism thoroughly first, then tell you why you shouldn’t go down the path of “increasing the bootstrap capacitor.”
Your direction is correct: this is bootstrap starvation. When the SPWM modulation index is pulled to 1, the duty cycle in the sinusoidal peak region approaches 100%, the low-side switch hardly turns on in any carrier cycle, there is no replenishment window for the bootstrap capacitor, VDDA−VSSA keeps dropping, and once it falls below 8.2 V (the UCC21520DWR is the 8 V UVLO version), the driver shuts off and the waveform collapses in a chunk — fixed-duty PWM has a low-side window every cycle, so it is clean. The logic is completely self-consistent.
But once you finish the math, you’ll see the capacitor isn’t the bottleneck at all:
0.45 V versus 2.6 V — nearly an order of magnitude of headroom. The capacitance is sufficient; making it larger won’t help.
So where does the charge go? Looking at Figure 3, one part caught my eye: the bootstrap diode D7 is an RS1M with a trr of about 500 ns. Your bus is rectified high voltage; every rising edge of the SW node is instantly pulled to several hundred volts, and during reverse recovery this slow diode pulls charge backward from VDDA to 12 V — stealing once on every switching edge, stealing the whole time. This perfectly explains both of your observations at once:
Suggested order of action:
This is a pitfall I’ve hit myself—the waveforms were almost identical. Fixed PWM was fine, but as soon as I switched to SPWM, a chunk was missing at the peak.
At first I also suspected the charging time wasn’t enough, so I lowered the bootstrap resistor from 10 Ω to 2.2 Ω and increased the capacitor from 0.47 µF to 2.2 µF. The notch got a little shallower, but it was still there when I pushed the modulation index to 1. Later I used a differential probe to measure VDDB with respect to VS and saw the voltage during the peak steadily dropping. Once it fell below the UVLO threshold, the drive shut off—the notch was being produced by UVLO. Only then did I understand that the low side has almost no conduction time near the peak, so the capacitor never gets a chance to charge.
While modifying it, I also hit a voltage-rating pitfall. The voltage rating of the bootstrap capacitor is chosen based on VDD, not the bus. When the high side is on, the voltage across the capacitor is still VDD; the entire capacitor’s potential is just lifted above the bus. It’s the bootstrap diode that has to be rated for the bus—it must withstand the entire bus voltage in reverse. I had these two mixed up at first, and the diode’s voltage rating wasn’t enough, so it leaked as soon as the bus voltage went high. Later I switched to a 100 V fast-recovery diode and it became stable. For a bus in the tens of volts, that’s enough; for a higher bus, leave another factor of two based on the bus. On the capacitor side, if VDD is 12 V, a 25 V rating is actually enough, but small X7R capacitors lose capacitance under DC bias, so a 50 V low-ESR part is more reassuring. After increasing the capacitor, you also need to check whether the diode can handle the charging inrush at power-up—don’t use too small a package.
In the end, I added an isolated power module for each high side, and the notch disappeared completely. If you don’t want to change the board, first limit the maximum modulation index to 0.9 and see whether the notch goes away—that’s a quick way to verify. To run at full modulation index, the bootstrap approach can’t hold up.
Bootstrap and a high modulation index are a bad marriage. The cap is a small battery that only gets charged while the low side is on. At the sine peak the high side is on for almost the whole switching period, so the low side is barely on at all. The cap drains into the driver quiescent current and the gate charge, the rail sags, UVLO trips, and you get a notch. There is nothing wrong with the SPWM signal. The bias scheme is the problem.
You can slow the sag with a bigger cap, a faster diode, and a smaller series resistor. You can shrink the notch by clamping the duty. You cannot make it vanish at m = 1 with a bootstrap, because the same cap has to be big enough to ride through the peak and small enough to recharge in the sliver of low-side time that is left. Those two conditions converge on zero.
For a one-off, a small isolated module per high-side driver is the least painful fix. Pick one with low isolation capacitance, otherwise the common-mode current will bite you. For a product, use a driver with an integrated charge pump or design a proper floating bias supply. Bootstrap is fine for a buck or a half-bridge that never runs near 100% duty. A sine-modulated bridge is not that.
Just use an isolated power supply to power VDDA and VDDB, otherwise you won’t get any of the advantages of your isolated gate driver—you might as well use a regular gate driver.
Okay, thanks, boss—I’ll give it a try.
Okay boss, I’ll first try the version without modifying the board.
Okay boss, got it—learned something new.
Okay, thanks, boss.
